This invention relates generally to a self-test circuit for semiconductor memory devices and more particularly to a self-test circuit and method utilizing interlaced scanning for testing semiconductor memory devices.
Modern integrated circuits generally employ various types of built-in semiconductor memory devices for use in performing data processing. For example, a combination of large-scale and small-scale memory devices are employed in a typical digital signal processing circuit for processing a digital signal.
Moreover, advances in sub-micron processing technology have enabled memory devices to become highly integrated. Unfortunately, the high level of integration also causes the testing of memory devices built into integrated circuits to become difficult and time-consuming. Various kinds of errors can be produced due at least in part to the substantial number of combinations of memory cells possible in each memory device. Accordingly, the demand for a self-test circuit and method for effectively testing built-in memory devices has increased.
A prior art approach to testing built-in memory devices utilizes a built-in self-test (BIST). According to this approach, a self-test circuit for testing the memory device is fabricated onto the integrated circuit and testing of the built-in memory device is performed by the integrated circuit itself. The BIST approach has been widely used for testing built-in memory devices because of its relatively simple construction, as compared to that required for, as an example, self-testing logic blocks. Moreover, from a practical design standpoint, no substantial amount of additional hardware is required.
As further described hereinbelow with reference to FIG. 2 in the Detailed Description, one prior art BIST approach employs a conventional built-in self-test circuit utilizing multiplexers for testing a memory device. There are several drawbacks to this approach. First, the self-test circuit is applicable only to synchronous memory devices. Additional hardware components are required for testing asynchronous memory devices which require the data to be shifted serially. Second, the self-test circuit is limited to testing only the memory cells in the memory device and not logic blocks which are coupled to the memory cells in the memory device. Lastly, one multiplexer is required per bit line of memory.
As further described hereinbelow with reference to FIG. 3 in the Detailed Description, another prior art BIST approach employs a conventional built-in self-test circuit utilizing a scan chain to perform serial memory accesses for testing a memory device. According to this approach, input and output registers are successively coupled to form a scan chain. However, a delay of up to one clock cycle for each bit in a memory word must elapse before data read out from the memory device and stored into the output register is output by the scan chain. Consequently, high speed, asynchronous testing is not possible.
Therefore, there is a need for a self-test circuit and method for efficiently testing both synchronous and asynchronous memory devices without the attendant delay incurred by serially accessing each bit in a memory word.